The Federal Communications Commission (FCC) has allotted a spectrum of bandwidth in the 60 GHz frequency range (57 to 64 GHz). The Wireless Gigabit Alliance (WiGig) is targeting the standardization of this frequency band that will support data transmission rates up to 7 Gbps. Integrated circuits, formed in semiconductor die, offer high frequency operation in this millimeter wavelength range of frequencies. Some of these integrated circuits utilize Complementary Metal Oxide Semiconductor (CMOS), Silicon-Germanium (SiGe) or GaAs (Gallium Arsenide) technology to form the dice in these designs. At 60 GHz, achieving the desired parameters of gain in a transmitter is significantly influenced by the layout.
Cost is a driving force in electronic products. Integration of circuit has allowed many more devices into the die. In addition, massive computation is typically requires when operating wireless systems. This has forced analog designers to introduce their circuit techniques into 8 layer metal CMOS processes more geared for digital logic manipulation rather than analog functions. The intersection of high speed analog circuits (60 GHz) with massive digital blocks has introduced resistive losses that influence the analog designs greatly.
Conventional physical layout techniques in high frequency circuit design introduce unnecessary loss. Any technology being pushed to the limit, as in the design of 60 GHz transmitters, makes these losses more pronounced. These losses influence target objectives and can cause the chip or die to fail meeting the specifications. New layout techniques are required to overcome these losses.